Spartan®-6 LX FPGAs are optimized for applications that require the absolute lowest cost. Now with up to 42% less power consumption and a 12% increase in performance enabled by ISE® Design Suite, they provide up to 150K logic cells, integrated PCI Express® blocks, advanced memory support, 250MHz DSP slices, and 3.2Gbps low-power transceivers.

Spartan 6 LX150T Development Board

The Spartan-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous Spartan families, and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input lookup table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO?technology, poweroptimized high-speed serial transceiver blocks, PCI Express?compatible Endpoint blocks, advanced system-level power management modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a lowcost programmable alternative to custom ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution for high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components that enable designers to focus on innovation as soon as their development cycle begins.

Spartan-6 FPGA主要特性:

Spartan-6 Family:

Spartan-6 LX FPGA: Logic optimized

Spartan-6 LXT FPGA: High-speed serial connectivity

Designed for low cost

Multiple efficient integrated blocks

Optimized selection of I/O standards

Staggered pads

High-volume plastic wire-bonded packages

Low static and dynamic power

45 nm process optimized for cost and low power

Hibernate power-down mode for zero power

Suspend mode maintains state and configuration with multi-pin wake-up, control enhancement

Lower-power 1.0V core voltage (LX FPGAs, -1L only)

High performance 1.2V core voltage (LX and LXT

FPGAs, -2, -3, and -3N speed grades)

Multi-voltage, multi-standard SelectIO?interface banks

Up to 1,080 Mb/s data transfer rate per differential I/O

Selectable output drive, up to 24 mA per pin

3.3V to 1.2V I/O standards and protocols

Low-cost HSTL and SSTL memory interfaces

Hot swap compliance

Adjustable I/O slew rates to improve signal integrity

High-speed GTP serial transceivers in the LXT FPGAs

Up to 3.2 Gb/s

High-speed interfaces including: Serial ATA, Aurora,

1G Ethernet, PCI Express, OBSAI, CPRI, EPON, GPON, DisplayPort, and XAUI

Integrated Endpoint block for PCI Express designs (LXT)

Low-cost PCI?technology support compatible with the

33 MHz, 32- and 64-bit specification.

Efficient DSP48A1 slices

High-performance arithmetic and signal processing

Fast 18 x 18 multiplier and 48-bit accumulator

Pipelining and cascading capability

Pre-adder to assist filter applications

Integrated Memory Controller blocks

DDR, DDR2, DDR3, and LPDDR support

Data rates up to 800 Mb/s (12.8 Gb/s peak bandwidth)

Multi-port bus structure with independent FIFO to reduce design timing issues

Abundant logic resources with increased logic capacity

Optional shift register or distributed RAM support

Efficient 6-input LUTs improve performance and minimize power

LUT with dual flip-flops for pipeline centric applications

Block RAM with a wide range of granularity

Fast block RAM with byte write enable

18 Kb blocks that can be optionally programmed as two independent 9 Kb block RAMs

Clock Management Tile (CMT) for enhanced performance

Low noise, flexible clocking

Digital Clock Managers (DCMs) eliminate clock skew and duty cycle distortion

Phase-Locked Loops (PLLs) for low-jitter clocking

Frequency synthesis with simultaneous multiplication, division, and phase shifting

Sixteen low-skew global clock networks

Simplified configuration, supports low-cost standards

2-pin auto-detect configuration

Broad third-party SPI (up to x4) and NOR flash support

Feature rich Xilinx Platform Flash with JTAG

MultiBoot support for remote upgrade with multiple bitstreams, using watchdog protection

Enhanced security for design protection

Unique Device DNA identifier for design authentication

AES bitstream encryption in the larger devices

Faster embedded processing with enhanced, low cost, MicroBlaze?soft processor

Industry-leading IP and reference designs

Spartan- 6 FPGA系列产品:







图1.Spartan- 6 FPGA系列汽车娱乐框图



图2.Spartan- 6 FPGA系列平板显示器框图



图3.Spartan- 6 FPGA系列视频监视框图

Xilinx Spartan-6 LX150T开发板

The Xilinx Spartan-6 LX150T Development Kit provides a complete development platform for designing and verifying applications based on the Xilinx Spartan-6 LXT FPGA family. Available with the Spartan-6 LX150T, the kit enables designers to prototype high-performance designs with ease, while providing expandability and customization through the dual FMC LPC expansion slots.

The Spartan-6 LX150T system board is available with the LX150T device (XC6SLX150T-3FGG676). Serial gigabit transceiver interface (GTPs) provide connection to the on-chip PCI Express® x1 hard macro or a PCI Express x4 soft macro, one SFP connector, and a SATA Host interface. The system board includes DDR3 SDRAM, Flash memory, a 10/100/1000 Ethernet PHYs, and a serial port. Other board features include a USB port, a programmable LVDS clock, user switches, and LEDs. The board also provides two FMC LPC expansion slots, providing a total of 136 high-speed, single-ended and differential user I/O. FMC modules can be easily added to the board for additional application specific functions.

Xilinx Spartan-6 LX150T开发板主要特性:

FPGA

— Xilinx Spartan-6 XC6SLX150T-3FGG676C FPGA

I/O Connectors

— Two FMC LPC general-purpose I/O expansion connectors

— One SD card connector

— Avnet LCD Interface (ALI) connector

RocketIO™ GTP Transceiver Connectors

— One Small-Form Pluggable (SFP) cage

— Two transceivers supplied on an FMC connectors for use by an expansion module

— One PCI Express add-in card interface (4 lanes @ 2.5 Gbps)

— One SATA host connector

Memory

— 128 MB DDR3 SDRAM components

— 32 MB FLASH

Communication

— RS-232 serial port

— USB 2.0

— USB-RS232 Port

— 10/100/1000 Ethernet port

Power

— Regulated 5.0, 3.3, 2.5, 1.8, 1.5 and 1.2 V supply voltages derived from the PCI Express slot or an external 12 V supply

— SSTL2 Termination Regulators

— Point of Load Regulators for MGT supply rails

Configuration


— XCF32 and XCF08 Platform Flash Configuration Flash


— Xilinx Parallel Cable IV or Platform USB Cable support for JTAG Programming/Configuration



图4.Xilinx Spartan-6 LX150T开发板外形图

Xilinx Spartan-6 LX150T开发板包括:

Xilinx Spartan-6 LX150T development board

12 V power supply

One license voucher for ISE® Design Suite: Logic Edition license (device-locked to Xilinx Spartan-6 LX150T FPGA)

Getting Started Guide

Downloadable documentation and reference design



图5.Xilinx Spartan-6 LX150T开发板框图



图6.Xilinx Spartan-6 LX150T开发板电源框图



图7.Xilinx Spartan-6 LX150T开发板跨接器,插座和连接器分布图


Xilinx Spartan-6 LX150T开发板电路图见:
Xilinx Spartan-6 LX150T开发板电路图.pdf


Xilinx Spartan-6 LX150T开发板材料清单见:
Xilinx Spartan-6 LX150T开发板材料清单.pdf

详情请见:
http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf
和
https://www.em.avnet.com/Support%20And%20Downloads/xlx_s6_lx150t_dev-ug_rev1.2_120210.pdf
以及
https://www.em.avnet.com/Support%20And%20Downloads/xlx_s6_lx150t_dev-sch-revd090810.pd